jvm.chisel.testing
Co-simulation harness for jvm.chisel modules using Chisel’s native chisel3.simulator (peek/poke/expect/step) with the bundled svsim/Verilator backend.
Requires an external simulator on PATH (Verilator, or VCS). Facts that call simulate should be gated with (fact:global {:skip (not (env/program-exists? "verilator"))}) so they are reported skipped (not failed) when no backend is present.
A module is simulated by passing its builder thunk (the value returned by jvm.chisel/module, or any of the *-module generators) and a body that drives it. Ports are addressed by their io field name (a string). For sequential modules the body also gets step/reset! (synchronous reset).
Drive an entire oracle table inside one body: each simulate recompiles the design with Verilator (~seconds), so batch many stimuli per call.
expect-vec!
(expect-vec! ctx pname vals)Expect each lane of the Vec output port named pname to equal the corresponding value in vals (lane 0 = first element).
pack
(pack bits)Pack a seq of 0/1 bits into an integer, element 0 at the least-significant bit (matches the lsb-first convention of jvm.chisel.variant, whose kernels now live in foundation-embed).
poke-vec!
(poke-vec! ctx pname vals)Poke each lane of the Vec port named pname with the corresponding value in vals (lane 0 = first element). ctx is the map passed to a simulate body.
simulate
(simulate builder f)Elaborate and simulate builder (a jvm.chisel/module thunk), running (f ctx) inside the simulation context. ctx is a map:
:port (fn name -> Data) io field by string name :poke (fn port v -> nil) v: long/boolean :expect (fn port v -> nil) throws FailedExpectation on mismatch :peek (fn port -> long) current value as a long :step (fn [] -> nil) step the implicit clock once :reset! (fn [] -> nil) assert reset for one clock, then release
Returns whatever f returns. Recompiles the design with Verilator on every call, so batch stimuli inside one body.
unpack
(unpack x n)The inverse of pack: the low n bits of integer x as a vector of 0/1, element 0 = least-significant bit.
vec-el
(vec-el vec-port i)The i-th lane Data of a Chisel Vec port (static integer index).