jvm.chisel.emit
SystemVerilog emission and Verilator lint for jvm.chisel module builders.
Thin wrappers around jvm.chisel.internal/emit-system-verilog (the circt ChiselStage) plus an optional verilator --lint-only check. Emission is pure (no simulation), so these are cheap to run and give an inspectable netlist for any verified module.
lint!
(lint! path top & {:keys [throw? extra-args], :or {throw? true}})Run verilator --lint-only on the SV file at path with --top-module top. Returns the clojure.java.shell/sh map {:exit :out :err}. Throws ex-info on non-zero exit unless :throw? false. extra-args is a seq of additional verilator flags (e.g. ["-Wno-fatal"]).
spit-system-verilog
(spit-system-verilog builder path)Emit builder to path (creating parents). Returns path.
system-verilog
(system-verilog builder)(system-verilog builder chisel-args firtool-opts)Return the SystemVerilog source for builder (a jvm.chisel/module thunk) as a string. Optional chisel-args/firtool-opts are passed to ChiselStage.