jvm.chisel.internal

JVM interop boundary for jvm.chisel.

This is the only namespace that talks to Chisel/Scala. It centralises the three awkward parts of calling Chisel from Clojure:

  • Chisel’s public operators are Scala macros that expand to do_<mangled> methods taking an explicit chisel3.experimental.SourceInfo. We pass a single UnlocatableSourceInfo everywhere and reach the do_* methods through clojure.lang.Reflector (the receiver type varies per Data subtype, so a single reflective dispatch is the clean option).

  • Companion-object factories (UInt, Wire, Mux, …) and package-object helpers (fromIntToWidth, fromIntToLiteral, …) are fixed targets and are type-hinted.

  • Module bodies must run inside the module constructor, which Clojure cannot inject into. A tiny Java base (xt.chisel.DynModule) runs a callback in its constructor; module binds *module* around it so that io can register itself for port naming.

Reflection warnings are disabled for this namespace only: this is the one sanctioned reflective boundary.

*module*

dynamic

the DynModule currently being constructed (bound by module)

add

(add a b)

b

(b value)

boolean literal: (b true|false) -> true.B / false.B

band

(band a b)

bits

(bits)(bits n)

bits-at

(bits-at a hi lo)

bit range extract a(hi, lo)

bnot

(bnot a)

bool

(bool)

bor

(bor a b)

bulk-connect!

(bulk-connect! left right)

bundle

(bundle elts)

Bundle from an ordered map/seq of name Data pairs. Field access uses field; keyword lookup is intentionally not provided (a Chisel Record cannot also be a Clojure ILookup).

bxor

(bxor a b)

cat

(cat a)(cat a b)(cat a b & more)

concatenate (a ## b ## …) lsb-first by pairwise do_##

connect!

(connect! sink source)

emit-firrtl

(emit-firrtl builder)

emit-system-verilog

(emit-system-verilog builder)(emit-system-verilog builder chisel-args firtool-opts)

eq

(eq a b)

field

(field rec k)

access a bundle/record field by name

gt

(gt a b)

gte

(gte a b)

index

(index coll i)

index a Vec (static int or dynamic UInt) or bit-index a Bits value.

input

(input t)

io-data

(io-data t)

lt

(lt a b)

lte

(lte a b)

module

(module name body-fn)

Return a zero-arg builder thunk for a module named name. body-fn is a no-arg fn that constructs io/wiring. The module is only elaborated once the thunk is invoked inside ChiselStage (i.e. by emit-* or module-instance), because a module can only be built within a Chisel Builder context.

module-instance

(module-instance build-thunk)

Instantiate a module, i.e. Module(new Child(…)). build-thunk is the zero-arg builder returned by module.

mul

(mul a b)

mux

(mux c t f)

neq

(neq a b)

output

(output t)

raw-module

(raw-module name body-fn)

reg

(reg t)

reg-init

(reg-init t)

reg-next

(reg-next t)(reg-next t init)

register-io!

(register-io! m data name)

Called by io: name the IO and expose it on the module for port discovery.

s

(s value n)

signed literal: (s value width) -> value.S(width.W)

shl

(shl a n)

shr

(shr a n)

si

sint

(sint)(sint n)

sub

(sub a b)

suggest-name

(suggest-name d n)

u

(u value n)

unsigned literal: (u value width) -> value.U(width.W)

uint

(uint)(uint n)

vec-as-uint

(vec-as-uint coll)

VecInit(coll).asUInt — pack a seq of Bool/Bits into a UInt (lsb first).

vec-init

(vec-init coll)

VecInit(coll) — a chisel Vec from a seq of Data (supports dynamic indexing).

vec-type

(vec-type n t)

Vec type constructor: (vec-type n t) -> Vec(n, t)

when-context

(when-context condition body-fn)

when-else

(when-else condition then-fn else-fn)

width

(width n)

integer width -> chisel Width

wire

(wire t)