jvm.chisel

A thin, direct mapping of Chisel primitives into Clojure.

Every public function/macro maps straight onto the corresponding Chisel primitive and Chisel performs the elaboration; there is no intermediate hardware representation. The only non-trivial machinery (implicits, symbolic JVM method names, module constructor scope, emission) lives in jvm.chisel.internal.

Clojure function  ->  corresponding Chisel primitive  ->  Chisel elaboration

Example: see src-lang/chisel/examples/predicate_eq.clj.

add

(add a b)

and

(and a b)

bitwise/logical AND

b

(b value)

boolean literal (b true|false)

bits

(bits)(bits w)

Bits type. (bits) or (bits width)

bits-at

(bits-at a hi lo)

bit range extract a(hi, lo)

bool

(bool)

Bool type.

bulk-connect!

(bulk-connect! left right)

(bulk-connect! left right) -> left <> right

bundle

(bundle elts)

Bundle (Record) from an ordered map/seq of name Data pairs. Read fields with field.

cat

(cat a)(cat a b)(cat a b & more)

concatenate (a ## b ## …)

connect!

(connect! sink source)

(connect! sink source) -> sink := source

emit-firrtl

(emit-firrtl mod)

Elaborate and emit FIRRTL (no external toolchain required).

emit-system-verilog

(emit-system-verilog mod)(emit-system-verilog mod chisel-args firtool-opts)

Elaborate and emit SystemVerilog. Requires a version-matched firtool (CIRCT); Chisel bundles a resolver that fetches one if absent.

eq

(eq a b)

field

(field rec k)

access a bundle field by name, e.g. (field io :values)

gt

(gt a b)

gte

(gte a b)

index

(index coll i)

index a Vec or bit-index a Bits value (static int or dynamic UInt)

input

(input t)

io

(io t)

Top-level module IO. When called inside module, registers itself as the module’s IO (named “io”) so Chisel can discover and name the ports.

lt

(lt a b)

lte

(lte a b)

module

(module opts body-fn)

Define a Chisel module. opts carries :name (and :raw? for an explicit clock/reset RawModule). body-fn is a no-arg fn that builds io/wiring. Returns the module instance (pass to emit-system-verilog).

module-instance

(module-instance build-thunk)

Instantiate a module, i.e. Module(new Child(…)). build-thunk returns the module (e.g. (fn [](module …))).

mul

(mul a b)

mux

(mux c t f)

(mux condition true-value false-value)

neq

(neq a b)

not

(not a)

bitwise/logical NOT

or

(or a b)

bitwise/logical OR

output

(output t)

reg

(reg t)

reg-init

(reg-init t)

reg-next

(reg-next t)(reg-next t reset)

RegNext. (reg-next t) or (reg-next t reset-value)

s

(s value w)

signed literal (s value width)

shl

(shl a n)

shr

(shr a n)

sint

(sint)(sint w)

SInt type. (sint) or (sint width)

sub

(sub a b)

u

(u value w)

unsigned literal (u value width)

uint

(uint)(uint w)

UInt type. (uint) or (uint width) -> UInt / UInt(width.W)

vec

(vec n t)

Vec type. (vec n element-type) -> Vec(n, t)

vec-as-uint

(vec-as-uint coll)

pack a seq of Bool/Bits into a UInt (VecInit(…).asUInt), lsb first

vec-init

(vec-init coll)

build a chisel Vec from a seq of Data (VecInit), dynamically indexable

when

macro

(when condition & body)

Chisel when conditional construction. Body runs in the when context.

when-else

macro

(when-else condition then else)

Chisel when/otherwise. Single-form then and else bodies.

wire

(wire t)

xor

(xor a b)

bitwise XOR