hara.model.annex.spec-verilog
!.verilog
macro
(!.verilog & body)always.verilog
macro
(always.verilog & body)assign.verilog
macro
(assign.verilog & body)break
macro
def$.verilog
macro
(def$.verilog & body)def.verilog
macro
(def.verilog & body)defabstract.verilog
macro
(defabstract.verilog & body)defgen.verilog
macro
(defgen.verilog & body)defglobal.verilog
macro
(defglobal.verilog & body)defmacro.verilog
macro
(defmacro.verilog & body)defn-.verilog
macro
(defn-.verilog & body)defn.verilog
macro
(defn.verilog & body)defptr.verilog
macro
(defptr.verilog & body)defrun.verilog
macro
(defrun.verilog & body)deftemp.verilog
macro
(deftemp.verilog & body)initial.verilog
macro
(initial.verilog & body)inout.verilog
macro
(inout.verilog & body)input.verilog
macro
(input.verilog & body)localparam.verilog
macro
(localparam.verilog & body)output.verilog
macro
(output.verilog & body)parameter.verilog
macro
(parameter.verilog & body)reg.verilog
macro
(reg.verilog & body)return
macro
tf-concatenation
added in 4.0
(tf-concatenation [_ & args])transforms concatenation {a, b}
tf-non-blocking
added in 4.0
(tf-non-blocking [_ left right])transforms non-blocking assignment <=
tf-port
added in 4.0
(tf-port dir [_ & args])transforms port declarations (input, output, inout)
wire.verilog
macro
(wire.verilog & body)